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FPGA-Systeme architekturneutral entwerfen

29. Juni 2007, 13:36 Uhr | Roger Do

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Fortsetzung des Artikels von Teil 2

           Zweitakt-RAM

ARCHITECTURE rtl OF RAM_read_first_two_clk IS
— Signal declarations
TYPE mem_type IS ARRAY (8191 DOWNTO 0)
OF STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL mem : mem_type;
BEGIN
PROCESS(CLK_A)
BEGIN
IF (CLK_A’EVENT AND CLKA = ‘1’) THEN
   IF Write_Enable = ‘1’ THEN
    mem(conv_integer(Address_A)) <=
     Data_In_A;
   END IF;
   Data_0Out_A <=
   mem(conv_integer(Address_A));
  END IF;
END PROCESS;
PROCESS(CLK_B)
BEGIN
   IF (CLK_B’EVENT AND CLK_B = ‘1’) THEN
    Data_Out_B <= mem(conv_integer(Address_B));
   END IF;
END PROCESS;
END rtl;

ENTITY FAST_IO IS
    PORT( I: IN STD_ULOGIC;
         O: OUT STD_ULOGIC);
    END FAST_IO;
    ARCHITECTURE xilinx OF FAST_IO IS
    COMPONENT IBUF_GTL PORT (O : OUT STD_ULOGIC;
        I : IN STD_ULOGIC);
    END COMPONENT;
    BEGIN
        I0: IBUF_GTL PORT MAP( I => I, O => O);
    END xilinx;

Das Top-Level-File instanziert nur den Wrapper-File:

FOR (i=0; i < sub_in_width; i=i+1)
    BEGIN
        FAST_IO IO (.I(Data_In[i]),
        .O(Data_In_int[i]));
    END
    ENDGENERATE

Codebeispiel für einen Mutiplizierer/Addierer

module mult_add(Data_Out, Data_A, Data_B,
Data_C, clk, load);
parameter sub_in_width = 18;
parameter sub_out_width = 48;
input clk, load;
input signed[sub_in_width-1:0]
Data_A,Data_B;
input signed[sub_out_width-1:0] Data_C;
reg signed[sub_in_width-1:0]
reg_Data_A,reg_Data_B;
reg signed[sub_in_width-1:0]
reg_Data_A1,reg_Data_B1;
reg signed[sub_out_width-1:0] reg_Data_C;
output reg signed[sub_out_width-1:0]
Data_Out;
wire signed[sub_out_width-1:0] Result;
reg [sub_out_width-1:0] Mult_A;
always @ (posedge clk)
begin
    reg_Data_A <= Data_A;
    reg_Data_B <= Data_B;
    reg_Data_C <= Data_C;
    reg_Data_A1 <= reg_Data_A;
    reg_Data_B1 <= reg_Data_B;
    Mult_A <= reg_Data_A1 * reg_Data_B1;
    Data_Out <= Result;
end
assign Result = load ? reg_Data_C: Mult_A +
reg_Data_C;
endmodule