7 Key Changes, Analog Designers Will Need to Make

5. Current Density limits the Transmitter Output Power

Designers have already faced this challenge when working on planar geometries – sub 40 nm. However, FinFET skinny metals and minuscule VIAs impose even more stringent limits on the maximum current density. They have limited current carrying capability and therefore power amplifier designers may be forced to use wider wires and to increase the width of the transistors in order fit the required VIAs and contacts. Depending on the voltage levels, designers may also need to increase the wire spacing.

The resulting longer wires and larger gate area introduce parasitics, making interconnects one of the limiting factors in power amplifier design; this must be considered in conjunction with the usual efficiency and linearity trade-offs.

Surprises can be avoided by floor planning the amplifier early in the design phase, even when the desired output power is relatively modest – i.e. just a few milliwatts.

1. 7 Key Changes, Analog Designers Will Need to Make
2. 1. Do not Mix Devices Having Different Dimensions
3. 2. Use Repeatable Patterns
4. 3. Estimate Interconnect Parasitics From the Start
5. 4. Use Digital Calibration to Correct Analog Errors
6. 5. Current Density limits the Transmitter Output Power
7. 6. High Flicker Noise Corner Frequency
8. 7. Simulations Are Slow