7 Key Changes, Analog Designers Will Need to Make

3. Estimate Interconnect Parasitics From the Start

Analog designers generally introduce parasitic extraction only at a later stage of the design. They are included in schematic simulations only for high-speed circuits and are limited to sensitive nets; resistance is rarely a problem.

This does not work with FinFETs: wiring and RC layout related parasitics are in many ways the limiting factor for performance and must be considered from a very early stage. Metal and VIAs resistance is a lot higher and dominant than in a planar geometry. To some extent, running parasitic extracted simulations that do not estimate resistance gives optimistic results and can be considered a pointless exercise.

As analog blocks tend to use a limited number of transistors geometries, it is recommended to build a ‘library’ of layouts for these devices (this shall include low-level VIAs and interconnects). After RC extraction, the resulting sub-cells can be used to design analog blocks so that their RC components are included in the simulations from the start.

1. 7 Key Changes, Analog Designers Will Need to Make
2. 1. Do not Mix Devices Having Different Dimensions
3. 2. Use Repeatable Patterns
4. 3. Estimate Interconnect Parasitics From the Start
5. 4. Use Digital Calibration to Correct Analog Errors
6. 5. Current Density limits the Transmitter Output Power
7. 6. High Flicker Noise Corner Frequency
8. 7. Simulations Are Slow