From the basics to the prototype

I. RISC-V principles according to ISA specification

Application level according to [1]

A processor manual essentially documents the address directory of the sub-blocks and the range of functions in assembler language for the user. On the other hand, the RISC-V ISA specification [1] goes one level deeper: it documents the binary command structure with the asm-code and, in addition, the decision basis for the respective design. Without claiming to be exhaustive, a few basic aspects are summarized below.

Irrespective of the length of the application address space (32, 64 or 128 bits), each RISC-V processor contains the basic instruction set marked with the suffix I. According to the specification, this basic instruction set does not have to be completely implemented in hardware. The Base Command Set I can be extended with a number of standard sets that do not have naming conflicts with each other. The general purpose extension G contains the sets M (multiplication), A (elementary bit manipulation), F (floating point calculation), D (double floating point calculation).

The basic commands measure 32-bit length. Instruction extensions can measure any integer multiple of 16 bits: the instruction length is specified with the first bits, and with long instructions in additional instruction sections (imm[u:l]). For resource-efficient applications, the compressed instruction sets can be used directly, but are not necessary. Each zero- or one-sequence transfers the processor to the error state: defective memory states are directly detected.

Since little-endian byte order is widespread in the embedded segment,
it is also used by the RISC-V standard. big-endian order would have to be implemented by a proprietary extension. When moving command sequences between registers, this order must be kept in mind so that the arithmetic unit can correctly capture the command length. The standard provides a verified procedure for the transfer from memory to arithmetic register [4]. If an exception condition occurs synchronously with command execution, its RISC-V terms is exception, interrupts are called asynchronous exception conditions. An exception can trap the system.

The base set R32I counts 47 commands. It can replicate all standard extensions except bit manipulations A. The programming model counts 32 32-bit registers x0 to x31. x0 is not writable and carries the NULL, x1 should carry the response address of a call. The specification is called the used three-address format efficient, for the complete execution in one step 32 registers are typically necessary. Depending on the application, eight registers are sufficient for dynamic execution of the compressed 16-bit sequences: here R32E offers an economical variant with 16 registers.

The 32-bit commands occur in four archetypes R/S/I/U (Fig. 1, above). I stands for Register-Immediate-, R for Register-Register-Manipulations, S is a memory format, the U-format is suitable for generating constants (e.g. addresses). Address information is located in the same place in all commands to minimize errors. Intermediate values, e.g. parameterizations, move between these classes into different command sections. The intermediate values almost always have a sign and are located as far to the left as possible in the sequence. Branches and jumps (B/J for Branch/Jump) are similar to S/U, the intermediate values are additionally divided into subsequences. Branches are based on the direct arithmetic comparison of two register entries. To increase reliability, RISC-V always locates the sign of an intermediate value in bit 31.

The basic commands never trigger an arithmetic exception. A buffer overflow test is not executed as a separate command, since it is handled more efficiently as an additional branch to the addition.

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In addition to the basic arithmetic operations, R32I also includes two fence commands to synchronize hardware threads* in an execution environment, elementary test and status commands (CSR), and timer and execution control (call and break).

RV32E is an additional 32-bit architecture for 16 register x0-x15 applications. When a command calls a missing register (x16-x31), it triggers an exception with an "illegal instruction" response. Possible default extensions for R32VE are M, A, and C.

The default extension M (Figure 1, below) contains separate commands for multiplication and division that are executed in archetype R. The default extension is M (Figure 1, below). Division by zero is the only statement in the standard instruction set that converts an exception to a trap. The exception is in an additional branch is executed after the multiplication.

Under certain conditions, the compressed R32E commands can be used. Due to the readability, compression was implemented one-to-one: just for debugging, another potentially nested compression would be too complex. The compression set should also be understood as a supplementary command library, a closed application in R32E is generally not possible. The specified compression distinguishes RISC-V from common embedded segment formats such as Arm v8. It is intended to provide a performance gain by reducing cache-miss with the shorter machine command. In a practical example this resulted in a similar performance as with double instruction memory [5].

1. From the basics to the prototype
2. I. RISC-V principles according to ISA specification
3. I. Behaviour in the environment
4. I. Interrupt and extension model
5. II. Design and verification according to DVCon Europe
6. III. Prototyping with the Vega-board
7. III. SDK components
8. IV. Conclusion