From the basics to the prototype

IV. Conclusion

RISC-V specification and platforms in software and hardware are currently suitable for the initial implementation of a c-code, its functional check and static analyses.  

Without a traceable RISC chip, the user will have to consider an external simulator or FPGA emulator. Furthermore, it is not clear whether the pulp-c compiler can be configured to use the compressed bit sequences. Nothing is documented in the generic place (readme.txt, internet search). The compression would have to be set in the c-program at inline-asm level by directly programming the corresponding command set (e.g. C.asm-command regx, regy).
 
The Vega-board with the restricted tool chain on the RISC-V side is therefore not a fully-fledged RISC-V laboratory on chip level at first. A realistic scenario is the development of a complex application on the arm side, with subsequent porting for a more efficient implementation on the RISC side. (ct)

Literature

[1] The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2, Editors Andrew Waterman and Krste Asanović, RISC-V Foundation, May 2017.

[2] The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.10, Editors Andrew Waterman and Krste Asanovic, RISC-V Foundation, May 2017.

[3] DVCon Europe Tutorial 7 - Tutorial on RISC-V Design and Verification

[4] The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2, Page 7, Editors Andrew Waterman and Krste Asanović, RISC-V Foundation, May 2017.

[5] Andrew Waterman. Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed. Master's thesis, University of California, Berkeley, 2011.

[6] RISC-V External debug support version 0.13.1

[7] VEGA SDK Manual - Getting Started with RV32M1 SDK (ARM)

[8] PULP GNU Toolchain

[9] arm GNU Toolchain

[10] VEGA SDK Manual - Multicore Application Report

[11] RISC-V Tutorial, HiPEAC2019, Valencia

[12] RV32M1 Series Reference Manual

[13] html" href="https://www.elektroniknet.de/design-elektronik/messen-testen/von-den-grundlagen-bis-zum-prototyp-163213.html">Design-Praxis RISC-V: Von den Grundlagen bis zum Prototyp, primary publication in german language.

** Before translating with the build script, it is recommended to use an execution of the clean script at the Arm part.

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1. From the basics to the prototype
2. I. RISC-V principles according to ISA specification
3. I. Behaviour in the environment
4. I. Interrupt and extension model
5. II. Design and verification according to DVCon Europe
6. III. Prototyping with the Vega-board
7. III. SDK components
8. IV. Conclusion