Keynote Speakers ew conference

Dr. Daniel Kästner, AbsInt Angewandte Informatik

Track Keynote: Taming timing – combining static analysis with non-intrusive tracing to compute WCET bounds on multicore processors (Tuesday, 02 March 2021, 16:15 - 16:45)

For safety-relevant real-time applications, worst-case execution time (WCET) bounds have to be determined in order to demonstrate deadline adherence. For timing predictable microprocessors, worst-case execution time guarantees can be computed by static WCET analysis. Hybrid WCET analysis is a solution for covering effects from accesses to interference channels of multicore processors. We present a hybrid method that combines static analysis with non-intrusive instruction-level tracing to automatically compute WCET bounds - including interference effects. This article gives a brief overview of static WCET analysis and introduces the concept of non-intrusive hybrid WCET analysis, using the Infineon AURIX as a reference architecture. A particular focus is on an integrated solution for hybrid WCET analysis which can request program flow trace information for the code snippets under analysis directly from the emulation hardware. Experimental results on industry-relevant code are reported.