Next-generation zonal architectures will build the foundation for truly autonomous vehicles. This electric/electronic (E/E) architecture will rely on highly integrated systems on chip (SoCs) that are connected via high-bandwidth in-vehicle networks.
A zonal architecture includes multi-functional zonal controllers, which are configurable devices that can be used for various functions like camera, radar or other dedicated processing tasks. The zonal controllers are connected via a high-speed Ethernet backbone to transfer the data to a (redundant) central compute unit.
Intelligent gateways route the data between the central compute unit, zonal controllers and sensors to enable high-resolution (raw) sensor data processing.
The proximity of the zonal controllers to the sensors or actuators helps to reduce the cable length, which further improves the bandwidth. Since the data of sensors mainly needs to be transferred in one direction (downstream) an asynchronous data transfer instead of full duplex data transfer is sufficient. Hence various interface options from serializer/deserializer (SerDes) like PCIe, MIPI to Automotive Ethernet are currently in discussion to connect the sensor to the zonal controller.
Depending on the sensor stack and driving functions, the zonal architecture also can be adapted to different vehicle classes by scaling the number of sensors, zonal controllers and gateways.
For sensor applications, there are various use cases where the sensor processing takes place – either in the smart sensor or at the central compute unit. For smart sensor applications, the sensor pre-processing is done either in the smart sensor or at the zonal controller, which helps to significantly reduce the amount of data that needs to be transmitted to the central compute unit. For raw sensor fusion including AI, all the processing is done in the central compute unit, which usually provides hundreds of TOPS compute power.
With the Cadence Tensilica AI Platform, Cadence provides a solution that can be scaled from 0.25 to hundreds of TOPS. Especially high-performance SoCs for the central compute unit consume a lot of power, which can be in the range of 500 watts. Hence these chips are leveraging water cooling methods as a more effective way to handle issues with heat dissipation. As this is a multiphysics system, electrothermal analysis including computational fluid dynamics (CFD) is needed to design, analyze and optimize the system.
By integrating multiple functions into high-performance SoCs, zonal architectures will also enable OEMs to consolidate ECUs and significantly save cost. However, there are a number of challenges with zonal architectures that need to be solved, including very-efficient sensor and AI processing at the edge, high-speed in-vehicle networking, scalability, power consumption, electro-mechanical and thermal optimization, electromagnetic interference (EMI), functional safety, cost and more.
Under the theme »Intelligent System Design«, Cadence is presenting a number of solutions for advanced driver assistance systems (ADAS), infotainment, medical, audio, voice, speech and system analysis at its booth in hall 4, booth 122.
At embedded world 2022, Cadence is showcasing its latest Tensilica DSPs and design tools targeted for a wide variety of applications: