Efinix
»We were able to exceed our own expectations.«
Fortsetzung des Artikels von Teil 2
The Goal: become Number 3 in the market
FPGA manufacturers typically generate a high percentage of their revenue through distribution. Where is Efinix today and what are the goals?
It is the same for us, Efinix also does its main business through its distributors. We are continuously expanding our distribution network, because our goal is to quickly catch up to the number 3 FPGA supplier in order to be able to place ourselves among the top 3 in the longer term.
An ambitious goal...
Yes, but thanks to our unique FPGA architecture, we believe we are in a position to achieve it. Because with this architecture we can also serve other markets, precisely those that value low power dissipation combined with high computing power. A great many end products need to become more intelligent and independent of the cloud, and still have low power dissipation. With today's FPGAs, this is a challenge because the FPGA either has low power dissipation but then lacks the corresponding speed, or the FPGA has the corresponding speed but requires too much power.
Low power dissipation is a special feature that Lattice has long been committed to. Is this a problem for Efinix?
No. We are different from all manufacturers who have taken low power as their banner. Here's how: With our Quantum technology, whether small or large FPGAs with up to one million logic elements, we can always rely on the same architecture, which is characterized by low power dissipation at high speeds, and at a commercially interesting price. I see the fact that other FPGA vendors are also focusing on "low power" as additional confirmation of our strategy. I am convinced that our Quantum architecture can help to meet these requirements. For example, when it comes to edge applications with artificial intelligence, these are precisely the requirements that we can serve.
We will also achieve the goals we have set ourselves in the automotive market. We have already taken the first step: We are currently offering the devices in our Trion family "T13/20F169Q4" and "T13/20F256Q4" as AEC-Q100 devices, and they are already being used in the automotive environment. However, we will also offer components from the Titanium family as AEC-Q100 variants, and we will also have our software certified in accordance with ISO 26262.
What is Efinix's position on SoC approaches?
Today's SoCs are typically based on the combination of ARM processors and FPGA resources, which is where the current FPGA market leaders are focused. Bringing a product of this scale to market means a very large investment in R&D as well as in applications to equip the product with an appropriate Eco-system. We are taking a different approach: for example, we are offering the implementation of a RISC-V processor as a soft IP that can be used on demand, on the assumption that this processor will become more popular.
At present, ARM is ahead by a wide margin, why do you think RISC-V will still succeed?
As you already mentioned yourself, more and more FPGA vendors offer the RISC-V core for their FPGAs. And if you look around the market, you will find more and more applications that have RISC-V embedded. The core is also being integrated into ASICs and standard products, which speaks for itself.
And that's exactly why we support this movement and put our faith in RISC-V. Our RISC-V-IP has been enhanced in the latest version to include a floating point unit, custom instructions and a LINUX MMU. We are pursuing an extensive roadmap regarding our RISC-V capabilities, including multicore and AI approaches. This means that we can already cover many cases that are implemented today with hard-wired processor/FPGA solutions.
It must be clear to everyone: many developers do not need a processor with 600 or 1000 MHz at all. They may be able to achieve a fast "proof of concept" with this, but when it comes to a system that is really to be produced, then it is a matter of economic considerations and optimized power dissipation. And that's exactly when a soft IP in our Titanium family can help. With it, speeds of up to 350 MHz are achievable, with optimized power dissipation at the same time. With our RAP approach, i.e. a reconfigurable accelerator platform, the developer can build on a predefined concept in which the areas of a C program that require higher computing power can be implemented in hardware. For example, from the video area, where we have, for example, outsourced filters as well as CNNs to the accelerator area. A very efficient system is available here via standard connections, such as AXI to DMA and memory.
We also offer our Titanium FPGAs as SoCs with integrated HyperRam as well as SPI Flash. This means that in a 5.5 x 5.5 mm² package all components are integrated that a system needs: Memory to swap out data, as well as an SPI Flash to boot the device. A Soft-IP RISC-V processor can use the HyperRam as memory.
For developers who need higher clock rates on the processor side, we will be able to offer this in the future. The future is very exciting!
- »We were able to exceed our own expectations.«
- Using standard processes brings advantages
- The Goal: become Number 3 in the market
- Hard- versus Soft-IP
