Smaller Structures, More Complex Systems – and Supply Bottlenecks

Chip designers and semiconductor manufacturers will continue to face growing challenges in 2022. So their EDA tools – and EDA vendors – face multiple challenges, as Joseph Sawicki, Executive Vice President, Siemens Digital Industries Software, explains in an interview.

?     What new features or tools can Chip/SoC designers and semiconductor manufacturers expect this year?

!     Joseph Sawicki: Production diagnostics and yield learning is an emerging set of capabilities that is shown to have a material impact on both yield ramp and mature product yield. Here what we do is take the production fail logs and combine them with physical analysis and machine learning to enable the determination of particular manufacturing hotspots that can then be tweaked to achieve better yield. We have had a number of customer using this as a standard part of their manufacturing process but have seen a great increase in interest as a result of the supply chain issues the industry is experiencing this year. In 2021, we saw impressive growth in our Tessent silicon lifecycle/embedded analytics line, and we expect that will increase in 2022.

Embedded analytics is an area we pioneered a few years ago with MissionMode and have solidified our leadership with UltraSoC. Tessent Embedded Analytics allows companies to embed monitoring IP into an IC and track/analyze a growing number of attributes, such as power, performance, safety and security of an IC through that IC’s lifetime. From a system perspective, it allows companies to do things like preventative maintenance. From a semiconductor engineering perspective, it provides a feedback loop to help deliver better next-generation products. For certain applications, such as automotive, aerospace, datacenter and communications – having this ability is pretty cool.

?     Will »More than Moore« become the standard this year?

!     Sawicki: I think that we’ll definitely see more 2.5D and 3D IC design starts, but I think it’s quite a ways off from becoming, as you say, »the standard«. We also have to take into account the current chip shortage and backlog in capacity. It actually takes more chips to make a 3D IC, and then capacity is needed to put those ICs in an advanced package.

Für Anwendungen, bei denen Unternehmen nicht gleich auf den modernsten That said, for applications where companies don’t want to jump to the leading-edge node or require heterogenous integration, the infrastructure is now in place to make it a more viable option. Siemens EDA is the leader in design wins with our 3D IC solution.

?     How important will AI become for EDA tools?

!     Sawicki: AI/ML is becoming a standard part of the EDA architectural tool set, right up there with linear solvers and scan lines. It’s being used ubiquitously in tools, and that’s because EDA is dealing with very large data sets with many opportunities to place algorithms that can discern relationships within that data; thus, can aid in productivity or device performance.

?     SoCs for AI and ML applications have special requirements. What new capabilities must EDA tools offer in the future?

!     Sawicki: AI/ML architectures demand innovation around two axis for EDA.

• First, is that the regularity of these designs puts a premium on techniques that can leverage that regularity for greater design efficiency – whether that be designing compilers to much more quickly move these designs into verification or hierarchical test techniques that can greatly increase the efficiency of both test and applying production test on the manufacturing line.
• Second, are new techniques that allow for the important aspects of architectural exploration that allow for an optimum power curve operation architecture to be put in particularly in edge-based AI chips. Here high-level synthesis has come into play, as it allows designers to do architectural exploration with a very fast and productive path to RTL and to move into traditional parts of the design flow.

?     Where do you see the biggest growth opportunities for the EDA industry?

!     Sawicki: Growth will concentrate in areas that solve the three biggest problems the design community has to deal with as we continue to evolve semiconductor technology.

• The first problem area with an opportunity for EDA growth is in technology scaling – helping the industry develop and design with the next monolithic process technology node and with making 2.5D and 3D and even silicon photonics a more viable option for mainstream customers.
• The second problem area with an opportunity for EDA growth is design scaling – helping customers manage the exponential complexity of today’s IC designs. A jump in abstraction is long overdue. We are helping customers by enabling them to move the level of abstraction up to the C-level, so design teams can more quickly develop PPA-efficient IC architectures. And we are helping them by integrating AI/ML in our tools so they can produce better results faster.
• The third area of growth for EDA will come from system scaling. As more systems companies strive to own more of their own value, they are designing their own ICs inhouse as well as the rest of the system. This allows them to differentiate their products greatly, protect their own IP to fend off fast followers and improve overall margins. They need solutions that look at the entire system from IC, to package, to PCB to software and even mechanical. They are looking for solutions that will help them develop a comprehensive digital twin and test it extensively before manufacturing the system. And they even want to extend that into ways to improve the manufacturing and entire lifecycle of the system. It’s one of the reasons silicon lifecycle management is such a hot topic right now, especially in the EDA world. Customers can use the IC at the heart of the system to detect problems and gather data to build better products faster. Siemens has an unmatched portfolio for this that can’t be touched by our competitors in EDA or in PLM.

?     What new problems or challenges may arise?

!     Sawicki: The supply chain issue and the distortion that brings into the market is difficult headwind to navigate. Clearly the trade frictions that are currently occurring also provide a headwind.

Joseph Sawicki

is a leading expert in IC nanometer design and manufacturing challenges. Formerly responsible for Mentor's industry-leading design-to-silicon products, including the Calibre physical verification and DFM platform and Mentor's Tessent design-for-test product line, Sawicki now oversees all business units in the Siemens EDA IC segment.

Sawicki joined Mentor Graphics in 1990 and has held previous positions in applications engineering, sales, marketing, and management. He holds a BSEE from the University of Rochester, an MBA from Northeastern University's High Technology Program, and has completed the Harvard Business School Advanced Management Program.