Schwerpunkte

Enhanced connectivity for Arm and x86

SGET publishes SMARC 2.1.1 specification

30. Juni 2021, 09:30 Uhr   |  Tobias Schlichtmeier

SGET publishes SMARC 2.1.1 specification
© SGET

With the new specification, developers gain the freedom to SerDes signaling over PCIe for GbE as well as full USB-C support.

The Standardization Group for Embedded Technologies - SGET - has published the new design guide for the current SMARC 2.1.1 specification. It provides developers with up-to-date design guidance for SMARC boards. Read about the changes the specification will bring here.

With the new specification, developers gain the freedom to SerDes signaling over PCIe for GbE as well as full USB-C support. This allows them to implement USB 3.2 Gen1 and DisplayPort Alt Mode over a single USB interface. With the new release, SGET aims to future-proof the SMARC Computer-on-Module (CoM) standard - including the benefit of designing new technologies to be backward compatible.

"New technologies and interfaces require guidance to implement them on SMARC carrier board designs," explains Martin Unverdorben, chairman of the SMARC module team. In addition to the work on implementing new features and the new recommendations for the layout of high-speed interfaces, great emphasis was placed on the readability and layout of the Design Guide, adds Carsten Rebmann, editor of the SMARC Design Guide.

With the new SMARC Design Guide, SGET is making an important contribution to the standardization of the CoM market for arm-based processors. However, x86 designs should also benefit from the new specification.

This is new in the Design Guide 2.1.1

SMARC Design Guide 2.1.1 includes a new chapter on SerDes implementations and provides more examples of full-featured USB-C implementations, including DisplayPort Alt Mode, as well as updated and expanded options for display interfaces. In addition, the module power supply chapter has been optimized to better explain the power-up process and the four separate power domains. New chapters have been added to implement the RESET_OUT signal and demonstrate the higher impact of via stubs due to high-speed signals, as well as additional via loss simulations. New considerations of SPI and eSPI topology complete the enhancements. The new design guide is available for download from the SGET homepage.

Auf Facebook teilen Auf Twitter teilen Auf Linkedin teilen Via Mail teilen

Das könnte Sie auch interessieren

Verwandte Artikel

SGET e.V.