Open source hardware and especially processors and SoCs based on RISC-V have caused a great response in the electronics industry. The number of RISC-V Foundation members is growing rapidly and its events are attracting exceptional interest worldwide. It is high time to take a closer look at the topic RISC-V and the most important implementations.
For a quick but well-founded introduction to the subject of RISC-V, Elektronik has won an expert from ETH Zurich as a speaker for a training course for professionals. Florian Zaruba, M. Sc., has been working for four years in the team of the PULP project (Parallel Ultra-Low-Power Processing) at ETH Zurich and is one of the main developers of the 64-bit RISC-V core Ariane.
On the first day of the Training for Professionals he will introduce the instruction set architecture RISC-V and present the PULP platform, especially the processor cores Zero-riscy, RI5CY and Ariane. The two cores RI5CY and Ariane are the first cores of the Core V family to be offered as »proven processor IP« by the OpenHW Group for industrial use.
Dr. Francesco Paci of Greenwaves Technologies will demonstrate on the second day of the Traning for Professionals how powerful and energy-saving a SoC with RISC-V cores can be. Greenwaves' SoC GAP8 is based on eight RISC-V cores from the PULP platform and was developed for AI applications. Dr. Paci will present the SoC GAP8 and show how it can be used to implement AI applications for a Convolutional Neural Network (CNN) - including an introduction to the development environment and tools.
The format of the Training for Professionals with a limited number of participants enables close contact with the trainers and an intensive exchange. Interested parties should therefore register in good time – and can benefit from an early booking discount until 2 October.