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Interview with Dr. Jo De Boeck, CTO Imec

„OxRAM can be an alternative to eFlash in some products“

1. Juni 2018, 10:34 Uhr | Frank Riemenschneider

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Fortsetzung des Artikels von Teil 1

„EUV can certainly make the design rules simpler“

DESIGN&ELEKTRONIK: Obviously EUV is a must for the coming up process nodes. May Engineers expect design rules to get much simpler than today?

Jo De Boeck: Yes, due to the significantly higher resolution it enables, EUV can certainly make the design rules – in addition to the process flows – simpler, e.g. for metals it can omit the use of blocks, increase metal widths and spaces.

DESIGN&ELEKTRONIK: Finding the right resist materials is one of the last big challenges for getting EUV into production. So far, researchers only get edges smooth if they use EUV exposures above a 20-millijoule/cm2 target. Which approach concerning finding a well suited resist material is the most promising?

Jo De Boeck: The question has to do with EUV stochastics, which has quickly become a hot topic in the industry. We have learned to think of stochastics in terms of it’s two separate, but related, effects: roughness and failures, which need to be reduced and elimiated, respectively. To reduce roughness and avoid failures, there are various novel resist approaches that suppliers are taking in addition to evolutions of the current chemically amplified resists (CAR). Many of which involve incorporating metals into the resist material or underlayers to increase absorption. They all have their pros and cons and it’s unclear at this point which strategy will yield the final solution (it may be a mix depending on application) However, resist alone is not likely to solve the problem and the ultimate solution to enable low roughness with zero stochastic defects will likely be a co-optimization of various parameters to include: resist and underlayer materials, imaging, computational lithography & photomask, track and scanner hardware, process integration, and post processing such as etch smoothing.

DESIGN&ELEKTRONIK: Another challenge are pellicles to protect EUV wafers from contamination. Imec is developing a pellicle using carbon nanotubes to provide the strength needed to withstand EUV exposures above 200 W while not preventing most of the light to travel through to the wafer. Is this approach similar or different from ASMLs approach?

Jo De Boeck: The approaches are quite different. The initial solution for the industry will likely be the approach ASML has been developing based on a thin film membrane. IMEC’s approach is to use a porous mesh of carbon nanotubes, which allows for high EUV transmission and very good mechanical strength and thermal durability. Our current investigations and developments focus on the chemical durability of these CNTs within the environment of the scanner.

DESIGN&ELEKTRONIK: Chip makers will also have to scale cell libraries to shrink chips. Imec is working on a three-track library that represents a 0.52x shrink of the seven-track libraries useed in 10-nm processes. Unfortunately it only leaves room for one FinFET per cell, down from three today. In addition, engineers can expect to face new design restrictions as cell tracks shrink, something already starting at 7-nm nodes. How to overcome these limitations?

Jo De Boeck: If all other design rules remain the same, a 3-track library represents 0.42x shrink from 7-track library. Library track height reduction is used to obtain target area scaling from 10nm downto 3nm because of relaxed pitch scaling. A 3-track library for the iN3 node (CPP 42, MP16) represents a 0.09x scaling compared to a 7-track library for the iN10 node (CPP 64, MP 48) whereas pitch scaling alone provides only 0.21x scaling. As one reduces track height, it gets increasingly challenging to make all internal connections between the devices in the standard cells. To overcome these challenges, innovative process integration techniques - called scaling boosters – are introduced. For ultra-low track cell libraries, we propose to use buried power rails in combination with complementary FET devices. Buried power rails remove the need to reserve two metal lines at local interconnect metal for power distribution, leaving all tracks available for connecting devices. Complementary FET devices (CFET) stack a P-device and N-device vertically, moving some of the connections between the devices in the vertical directions, in this way relieving wiring congestion.

However, as track height reduces, the area footprint available for active devices gets more and more limited. At 5T and less, it becomes extremely hard to integrate more than a single fin per device. To compensate the loss of drive several solutions are explored: Increasing the fin height increases drive currents, but also comes with added parasitic resistance and capacitance, limiting the effectiveness of fin height increase; Hence reducing parasitic resistance and capacitance by improving materials and processes is essential to improve the performance of taller single fin devices; Finally, lateral GAA nanosheets offer a more efficient use of the available footprint, providing more current per area in low-track cells.