Interview with Dr. Jo De Boeck, CTO Imec
„OxRAM can be an alternative to eFlash in some products“
Imec (Interuniversity Microelectronics Centre) is the leading european research institute for semiconductors,employing 3500 highly qualified scientists. In an exclusive interview with DESIGN&ELEKTRONIK CTO Dr. Jan de Boeck revealed the future of semiconductor chips, their manufacturing and memories.
DESIGN&ELEKTRONIK:Imec is talking about below 3 nm nodes, which seems to be very optimistic regarding mass production taking several challenges in consideration. First of all, FinFETs will achieve a limit. Which will be the last node using FinFETs and which kind of transistors will follow? Nanowires, event tunnel FETs, spin-wave transistors, a mixture of all of them on one die?
Jo De Boeck: Indeed FinFETs will achieve a limit. First from a power-performance point of view we will reach a point where the parasitic elements will take over and no aditional performance can be achieved at circuit level with a finFET architecture. Second from a leackage point of view we see the need to move to a device architecture with better electrostatic control of the gate which is the Gate all around or Nanosheet device architecture. We believe the transition to this architecture is related to the contacted pitch scaling and we place the transition to the 3nm node. This has been substantiated by a recent anouncement by Samsung on the choice for their 3nm node being a lateral Nansosheet type of device. Beyond that we do see indeed the emergence of hybrid technologies where different type of devices will be integrated on the same dye. We at imec are proposing 2 paths. The first one involves building nFET devices stacked on top pFET devices, both having nanosheet like channel. We call this device complementary FET called CFET and we position it as a promissing concept device after the 3 nm node. One of the benefits that the CFET brings is moving the N to P boudary in the vertical direction and thus providing significant area scaling benefits. A second approach is to sequentially stack different type of devices through wafer bonding techniques, which can be a promissing approch of stacking SRAM, I/O or Analog devices on standard logic. This approch will again lead to die level scaling and overall functionality improvements.
Jo De Boeck: We do see promissing devices that can be integrated with standard CMOS, including 2D based devices, and spin devices. These options will definitely add to overall system functionality improvements but will only come in around 6-10 years.
DESIGN&ELEKTRONIK: You can see the atomic limits ahead. A single arsenic atom, one of the larger elements used in semiconductors, measures about 1.2 Angstrom or 0,12 nm. Which is in your opineon the smallest node the industry can achieve? 10 Angstrom? 20 Angstrom?
Jo De Boeck: We should not mistakenly think that the numbers used in the node terminology refer to a critical dimension in the technology. They just suggest an overall deacrease in the device and inteconnect critical dimensions node to node. This being said probably the smallest critical dimension involved in a device is the gate oxide, it’s thickness is ~20 Angstroms. The second device dimesion is the channel dimension – the smaller cross sectional dimension cannot be scaled below ~ 40 Angstroms. In our roadmap the technology node that involves CFET corresponds to a node that the industry will likely call 1.4 nm or 14 A (14 Angstrom).
- „OxRAM can be an alternative to eFlash in some products“
- „EUV can certainly make the design rules simpler“
- Any flavor of RRAM + any flavor of selector is stopped in some companies due to trade-off between power and stability
- Disclosure
