At APEC and PCIM a lot of papers are discussing multilevel converters. I know you have been talking about it for a while.
You are right, and this brings me to a question I’ve been asked again and again: When do you bring out 600 volt devices? We don’t need to, thanks to David Perreault. This brilliant guy, a professor at MIT, came up with this concept of multilevel converters some five years ago.
If you have an AC waveform, you don’t have to block several hundred volts all the time, but only for a relatively short period of time; most of the time the voltage it’s much lower. So in a multilevel topology you use for example only one 100 volt device, if you have to block up to 100 volts, and two 100 volt devices in series, if you have to block a voltage between 100 and 200 volts, and so forth.
And there is another aspect. Let’s take for example our EPC2032. This 100 volt/48 amp GaN transistor has an on-resistance of 4 milliohms, while the best 600 volts Superjunction MOSFETs have some 40 milliohms for 50 amps. So if you take six of our 100 volt devices in series, you have a 40 percent lower on-resistance as one 600 volt part. And this in turn reduces the conduction losses by 40 percent. This is very significant, isn’t it?
Absolutely, but the control scheme for a multilevel converter is much more complicated, isn’t it?
That’s the point. A multilevel topology consists of multiple devices in a totem-pole configuration and a complicated control scheme with very exact timing and dead-time control. That’s why you haven’t seen it widely adopted yet, but meanwhile the control scheme has been worked out and is starting to get available. And if you are able to integrate all that onto one chip with the entire control scheme, then this comes down to an additional 10 cent 8-bit microcontroller that clocks the whole thing with 500 megahertz. But this might take another two or three years for us to get a fully-integrated multilevel device.
And then there are switched-capacitor converters which are coming on vogue, too.
The magnetics are the most bulky parts of a converter and the components with the highest losses. Minimizing them or even getting rid of them increases the power density.
Additionally, at the asymptote of a technology you have to take a lot of efforts to squeeze out the little rest of efficiency improvement. Vicor is doing a great job, their converters are fabulously engineered. But if you take a look inside their products, their topologies are so complicated using resonances at the input and the output, and so forth. By this they achieve these high efficiencies. But with GaN you can do the same while using a dumb buck converter.
But what’s about EMI at these high frequencies?
Actually, high frequencies are a friend of EMI, because with higher frequencies it gets much easier to attenuate these interferences with smaller filter components. Moreover, the biggest EMI problems when using MOSFETs are caused by ringing because of the parasitic inductances. But if you are able to minimize these stray inductances, and we do that with our chipscale packages as shown on our demonstration boards, then you have less problems with EMI.
One issue with adopting new technologies is always cost. You already reached cost parity from the solution standpoint. But now you have taken the next step, haven’t you?
Absolutely! From the device standpoint our current Gen5 products are lower in price as an equivalent silicon part with the same voltage rating and on-resistance. So the last argument in favor of silicon MOSFETs, the price of the device, has been swept away, and we are able to attack it directly in its homeland. And the next step is at hand, because with Gen7 we will migrate from 6 inch to 8 inch wafers which will lower the cost again significantly.
Alex, many thanks for taking the time.
The interview was conducted by Ralf Higgelke.