Dr. Michael Töpper, IZM
“We stand at the forefront in packaging!”
Fortsetzung des Artikels von Teil 1
Future goals of the PLC 2.0 project
What other goals has the PLC 2.0 project set itself?
First of all, the goal of the second consortium is to achieve a line width of 2 µm. However, we want to go to the limits of the fine-line structure, at least to a space of 1 µm. Then, undesirable effects such as the migration of copper into the dielectric increasingly occur. We want to investigate these processes in detail in order to be able to control them. I am confident, however, that we will be able to achieve 1 µm.
Is Germany a leader in this technology with IZM’s PLP line?
In global terms, we stand at the forefront, even if we have not yet reached the status that will answer all the questions of high-volume production.
When do you expect the first commercial line to be established?
We are holding initial talks about the transfer to a commercial production line. Production could initially start on smaller panels because high volumes are currently not yet needed in Europe. But the technology is also very interesting for special applications due to its high performance. And these companies need a manufacturer in Europe.
In Asia, Samsung has started up the first commercial PLP line to produce chips that will go into the Apple Watch.
Samsung certainly has a head start because the company has now been able to gain experience from current production. However, the lead is not very big.
Currently, many major IC manufacturers are busily developing fan-out panel level packaging techniques, as well as other advanced packaging techniques from heterogeneous integration to chiplets. Will they take some of the business away from companies such as ASE, Amkor and STATS ChipPAC that now do packaging and test?
That is a good question. It could be that outsourced semiconductor assembly and test (OSAT) between IC manufacturers and substrate manufacturers will come to an end. Intel’s recent announcement that it plans to provide power from the back of the wafer also suggests that the packaging world could change in the future. Flip chips would then no longer be possible without additional packaging processes.
The interview was conducted by Heinz Arnold.
Fraunhofer IZM-ASSID at productronica 2021: Hall B1, Booth 221
| IZM and panel level packaging |
|---|
| The Fraunhofer Institute for Reliability and Microintegration IZM coordinated the first Panel Level Packaging Consortium from 2016 to 2019. For its first run, the focus of the consortium was on the entire process chain in panel-level packaging: from assembly, molding, wiring, and cost modelling to standardization. With the second consortium launched for 2020–2022, this focus has shifted to die placement and embedding technology for ultra-fine-line wiring. This international cooperation again involves 17 partners from industry: Ajinomoto Fine-Techno, Amkor Technology, ASM Pacific Technology, AT&S Austria Technologie & Systemtechnik, Atotech, BASF, Corning Research & Development, Dupont, Evatec, Fujifilm Electronic Materials U.S.A., Intel, Meltex, Nagase ChemteX, Rena Technologies, Schmoll Maschinen, Showa Denko Materials, (formerly Hitachi Chemical Company) and Semsysco. |
- “We stand at the forefront in packaging!”
- Future goals of the PLC 2.0 project
