Elektroniknet Logo

Alliance with Chipbond

UMC invests in Advanced Packaging

Die Fab 12A von UMC im Tainan Science Park.
UMC's Fab 12A at the Tainan Science Park.

UMC has formed a strategic alliance with Chipbond Technology to gain a foothold in advanced packaging. Intel and TSMC are also investing in this technology.

Through a share swap, Taiwan's second largest foundry by far, UMC, plans to take a 9 percent stake in Chipbond, a provider of assembly and test services. Conversely, Chipond is expected to hold a 0.87 percent stake in UMC after the swap. One of Chipond's strengths is in packaging and testing flat panel driver ICs. UMC is one of the world's leading foundries for manufacturing these ICs. Currently, like so many, these IC types are in short supply. Wu Fei-jain, Chairman of UMC, expects the situation in this market sector to ease only by the end of 2022.

TSMC: $10 billion for adanved packaging fab

The world's largest foundry, TSMC, has been making great efforts to advance into advanced packaging, including chiplets technology, for several years now, but is not taking the route of cooperating with OSATs (Outsourced Semiconductor Assembly and Test), but is developing its own processes. As recently as June of this year, TSMC announced it was considering building a dedicated fab for advanced packaging processes in the US. TSMC is currently building a $10 billion advanced packaging fab in Miaoli County, Taiwan, where it plans to manufacture chips for customers such as Advanced Micro Devices and Google, starting next year. TSMC also operates advanced packaging and test facilities in Taoyuan, Hsinchu, Taichung and Tainan.

TSMC has consolidated its three advanced packaging technologies - lCoWoS, InFO and SoIC - under the name "3D Fabric". The latest packaging technology, "SoIC", is understood by TSMC as the integration of chiplets, also called heterogeneous integration.

Intel: Advanced Packaging supports Moore's Law

Advanced packaging also plays a significant role in Intel's race to catch up. Advanced packaging is essential for improving the performance of chips according to Moore's Law.  In June, Intel had presented its roadmap to the year 2025. In this context, CEO Pat Gelsinger had emphasized that not only the new gate all-around transistor type called "RibbonFET" and the new "PowerVia" interconnect technology were the prerequisites for Moore's Law to continue to apply. Without advanced packaging techniques, this goal could not be achieved, he said. These include the "EMIB" (Embedded Multi-Die Interconnect Bridge) and "Foveros" technologies, which Intel will continue to develop in different variants. At this level, Intel says the boundaries between the front-end and back-end processes, i.e. between wafer-level manufacturing and packaging, would blur, opening up new opportunities for die partitioning. The "Foveros Direct" and "Foveros Omni" variants should be ready for production from 2023.

Verwandte Artikel