RISC-V

Two new RISC-V specs for 2022

23. Juni 2022, 6:00 Uhr | James Bryant
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RISC-V International will announce two new specification approvals at embedded world. Efficient Trace for RISC-V (E-Trace) and RISC-V Supervisor Binary Interface (SBI).

The two new specification approvals by RISC-V International follow the 2021 announcements of 16 specifications representing more than 40 extensions, with more in the pipeline: a RISC-V Unified Extensible Firmware Interface (UEFI) specification and the RISC-V Zmmul multiply-only extension. Development and ratification of the two new specifications were led by Gajinder Panesar and Iain Robertson of Siemens.

»The RISC-V culture of contribution and collaboration continues to produce impressive results,« said Calista Redmond, CEO of RISC-V. »RISC-V members are leaders in the era of open compute, proving that collaboration accelerates innovation through shared investment while growing global opportunity.« »These new specifications will help accelerate embedded and large-system design,« said Mark Himelstein, CTO of RISC-V. »Debugging is one of the hardest things to do on a chip,« he explained. »E-Trace for RISC-V creates a standard and extremely efficient way to perform processor trace which is especially useful in embedded system design.«

E-Trace for RISC-V defines an approach to processor tracing that uses a branch trace, ideal for debugging any type of application from tiny embedded designs to super powerful computers. E-Trace for RISC-V documentation specifies the signals between the RISC-V core and the encoder (or ingress port), a compressed branch trace algorithm, and a packet format to encapsulate compressed branch trace information. »RISC-V SBI offers developers the ability to port supervisor-mode software across all RISC-V implementations, allowing developers to write something once and apply it everywhere.«

RISC-V specification for SBI describes a firmware layer between the hardware platform and the operating system kernel using an application binary interface in supervisor mode. This enables common platform services across all RISC-V operating system implementations. Additional specifications and expected to be announced soon.

The UEFI specification is designed to implement the existing UEFI standard on RISC-V platforms. UEFI connects an operating system to firmware and, in some applications, may replace basic input-output system (BIOS) software. The RISC-V Zmmul extension enables low-cost implementations that require multiplication operations but not division and is part of the RISC-V Unprivileged Specification. For many microcontroller applications, division operations are too infrequent to justify the cost of divider hardware. This extension will benefit simple FPGA soft cores in particular.

RISC-V International – an open standard, non-profit community with more than 2,800 RISC-V members across 70 countries – is hosting a pavilion of member-company innovations at embedded world (hall 1, booth 550). Showcase participants include Andes Technology; CAES, Cobham Gaisler; Canonical Ubuntu; Codasip; Codeplay; Digital Core Technologies; GreenWave Technologies; Imperas; OpenHW Group; SiFive; Syntacore; and Ventana Micro.

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