Technical Sessions at the Booth

11. April 2018, 14:42 Uhr | Harry Schubert
Jede Stunde ein technischer Vortrag auf der Messe Embedded World am Stand von Microsemi.
Hourly presentations on five technical topics at the Embedded World booth of Microsemi.
© Life and Times - Shutterstock

During Embedded World, Microsemi will be presenting lectures on five technical topics at its stand every day from 10.00 a.m. onwards.

Microsemi hosts five core sessions at Embedded World 2018 in hall 1 that you won’t want to miss. Come talk to the experts in the following areas:

  • PolarFire FPGA Solutions
    During this presentation, users will be introduced to the PolarFire FPGA family. The device architecture details, schedule of devices/packages, available IPs and demo designs will be discussed.
  • Introduction and Update on RISC-V
    Rick O’Connor from the RISC-V Foundation will present on the basics of RISC-V and the latest updates of the ISA and ecosystem. The benefits of the open instruction set architecture and the numerous RISC-V solutions available at embedded world will be explained.
  • Mi-V RISC-V Ecosystem
    Microsemi’s Mi-V RISC-V ecosystem components and roadmap will be presented during this talk. Experts will detail the available CPUs, example designs, boards, operating systems and more. Users will understand the benefits of using the Mi-V RISC-V ecosystem for their next design.
  • Machine Learning/Artificial Intelligence
    Hardus Richter from ASIC Design Services will explain the details of the multi-layer convolutional neural network CoreAI IP. Details will be shared on how the IP optimizes the FPGA fabric, DSP and memory resources for optimal performance per watt. Deep learning libraries such as Caffe or Lasagne can be extracted into the IP. Users will understand the wide breadth of applications which this machine learning IP could be targeted for.
  • Walnut Digital Security
    SecureRF will present the capabilities of its Walnut DSA security IP. Experts will explain how this IP allows one to securely boot a processor and verify digital signatures. In addition, firmware updates can be safely encrypted by leveraging crypto vector extensions of the soft RISC-V core in Microsemi FPGAs. All of these security demos run much faster than a hard processor could execute them because of the hardware acceleration of the IP.

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