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SIM-V Simulates Custom RISC-V Processors
The RISC-V instruction set serves as an excellent foundation for developing custom processors, making it a popular choice among companies seeking to design their own application-specific CPUs, such as DSPs or ASIPs.
However, the hardware design is just one aspect of the process; equally important is the target software that harnesses the custom extensions of the base architecture. To efficiently implement custom extensions, several key questions must be addressed.
Firstly, it is crucial to identify the hotspots within the target software that can be optimized through instruction set extensions. Once the hotspots have been identified, the optimal extension can be defined. Subsequently, the target software needs to undergo profiling, testing, and verification. This iterative design process continues until the final extension design has converged. However, testing and verifying custom RISC-V extensions can be arduous, particularly when integrating the custom processor into a complete System-on-Chip (SoC). The performance of full system simulations is determined by the slowest simulation model, making simulation performance a paramount consideration.
MachineWare GmbH, a German virtual prototyping company, has recently introduced SIM-V, a revolutionary RISC-V instruction set simulator. SIM-V not only boasts high simulation performance but also seamlessly integrates into existing simulation environments while offering easy customization options. To facilitate the design of custom RISC-V processors, MachineWare provides the SIM-V Extension SDK, empowering users to extend SIM-V with custom instructions, registers, and more. Starting from one of MachineWare's RISC-V reference models, which can already execute complex target software such as RTOS, Linux, or RISC-V Android, users can easily incorporate custom features to accelerate specific parts of the target software. The simulator generates detailed statistics, providing deep insights into target software execution on SIM-V and the utilization of custom extensions. Furthermore, the resulting processor model can be seamlessly integrated into various open and commercial simulation environments.
The resulting processor model can be integrated into many open and commercial simulation environments. MachineWare provides an IEEE standard SystemC TLM-2.0 integration and a TLM productivity library called VCML (Virtual Component Modeling Library), which is open-source. VCML comes with numerous free models and model building blocks, enabling swift setup of full system simulations. Additionally, VCML includes tool integrations that seamlessly integrate SIM-V with standard debuggers like GDB or Lauterbach’s Trace32. It also offers scripting support for integrating SIM-V into a Continuous Integration (CI) environment.
