One of the biggest advances in the new Mercedes A-Class is the MBUX system with innovative voice control and touch operation. What hardware is behind the "user experience"? We provide the answer.
The features of the MBUX (Mercedes-Benz User Experience) include three-dimensional digital displays, a touch screen, voice control and OTA updates.
A fundamental innovation compared to the previous infotainment system from Mercedes is the possibility of controlling the user interface directly via a touch screen and with the aid of wipe and zoom gestures. In the past, people relied either on voice commands, a touch control on the steering wheel or a touchpad between the seats. The touch surface on the steering wheel is no longer available, but the other two options are still available.
MBUX will celebrate its premiere in the brand-new A-Class, which will be released this year. The system will also be found in all future Mercedes vehicles. The system will first appear in the A-Class because it is aimed primarily at younger buyers who expect their car to provide the connectivity and user experience they have come to expect from their smartphones.
The infotainment system uses Nvidia's top-of-the-range Tegra Parker, which is designed for AI, UAV and car applications and supports hardware virtualization through arm virtualization enhancements (including the privileged HYP execution mode for executing a hypervisor). The operating system is an embedded Linux based on the Yocto Project.
Six CPU cores work on the chip: four Cortex-A57 from arm and two Denver cores, which were developed by Nvidia itself. In general, the L1I and L1D caches (128 KB + 64 KB) and the L2 buffer (2,048 KB) are quite large for two Denver cores. The four Cortex-A57 are equipped with 48+32 and 2 MB caches. The two clusters are coherent, which Nvidia achieves through a proprietary switching matrix. The Tegra has a 128-bit memory interface that works with LPDDR4-3200, transmits a maximum of 50 GB/s and supports error correction (ECC) from the memory controller.
The Denver CPU is ARMv8 compatible and delivers high processing power through an unusual technique: a dynamic command translation, which translates ARM instructions into micro-ops. Nvidia's Denver CPU can execute 64-bit ARMv8 code in two ways: either natively at a top speed of two instructions per clock cycle or by using dynamic code optimization, achieving a peak rate of seven micro-ops per clock cycle.
In order to deliver high computing power with as little energy as possible, Nvidia has chosen the dynamic translation approach. It's similar to what Transmeta did a decade ago. Unlike this design, Denver includes some hardware-based command decoders. This means that only frequently used routines need to be translated, which reduces the overhead caused by the translation.
The 6 CPUs are joined by 256 GPU-CUDA cores from Nvidia's "Pascal" generation. This microarchitecture is a further development of Maxwell and offers several advantages. The fourth generation of Delta Color Compression can now compress 4:1 and 8:1 in addition to an improved 2:1 compression. Furthermore, the GPU can automatically try out the different compression types and select the best one. Maxwell's architecture could statically distribute overlapping tasks (compute and graphics) to the GPU. However, this partitioning could only be changed after both tasks had been completed. For example, if one of the two tasks was finished earlier, the remaining one could not use the entire GPU, but had to be limited to its assigned portion. With Pascal, the assignment is now dynamic and can make full use of all GPU resources. The Simultaneous Multi-Projection (SMP) Block is a new hardware unit in the PolyMorph Engine at the end of the geometry pipeline and in front of the raster units. It allows the fast creation of different projections (angle of view on the image) in a single pass for the geometry data. Up to 16 different projections with the same viewpoint and two different projections with different distances on the x-axis can be calculated. The system has access to 8 GB RAM.
A smaller SoC, specifically a Tegra X1 with a big.LITTLE combination of four Cortex A53 and four Cortex A57 CPUs from arm, is used in the "Entry" and "Mid" equipment levels of the system. While usually arms Global Task Scheduling (GTS) is supported, so that all 8 cores can be used in parallel, Nvidia has implemented its own solution based on cluster migration. This means that either the Cortex A57 or Cortex A53 cores are active, but never both quad-core clusters at the same time. On the graphics side, the X1 contains 256 CUDA cores of the Maxwell generation.
The memory controller now supports LPDDR3 as well as LPDDR4 and thus enables a bandwidth of up to 25.6 GB/s (2x 32 bit LPDDR4-3200).
After Audi and other brands of the VW Group, Nvidia is now also very active at Mercedes with its Tegra SoCs. Obviously, Nvidia's objective advantage on the GPU side over competing architectures has also convinced in Stuttgart (the CPU clusters are certainly not "leading edge" on the SoC market).