From FPGAs to Structured ASICs to Custom ASICs

...lower hurdles for FPGAs

The programming problem is not really new in the FPGA world. Intel recently announced its One-API project, which is likely to lower the hurdles for FPGAs. What is the status quo here?

I can't give you any details now, but Intel will give you more information before the end of the year.

But the goal of this project is that a developer, no matter if he programs an FPGA, a CPU, a DSP or a GPU, can always use the same interface? So no more RTL?

Yes, that's right, the API becomes more or less completely hardware-agnostic. This means that the customer can use the hardware that best fits his application, but for the software developer it is almost irrelevant which hardware is used. That is at least the goal.

Intel has not only bought Altera, but also eASIC. A rather surprising step for me, because many companies, including Altera and Xilinx, have already tried this FPGA-to-ASIC approach and failed. I know that e.g. ZTE uses eASIC components, but still the question: Why does Intel think it will be more successful with this approach than others?

 There are two important cost issues with Structured ASICs: the actual Structured ASIC and the development of the necessary hard IP blocks, both very costly vectors. The stand-alone Structured ASIC companies have struggled to drive the volume to meet these costs. As part of Intel, it's different. Intel already has a huge IP portfolio and has enough resources to develop or buy more IP. This already solves one of the two problems.

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1. From FPGAs to Structured ASICs to Custom ASICs
2. ...lower hurdles for FPGAs
3. 5G opens up completely new possibilities...