Cheerful with Occasional Shadows

"Thunderbolt will hardly play a role..."

The industry does not agree on the extent to which possible compatibility with Thunderbolt plays a role in the embedded business. "Norbert Hauser, Vice President of Marketing at Kontron, is convinced that "Thunderbolt has never really made its way into the embedded industry and will therefore hardly play a role in the future. Jens Plachetka, Manager Board Platforms at Avnet Integrated, is more optimistic: "At the moment there isn't much demand, but Thunderbolt will become an important topic in the future". Daniel Piper, Head of Marketing Embedded IoT at Advantech Europe, cites possible reasons for this: "Thunderbolt in the sense of a miniPCIe-over-cable function for I/O connection can definitely play a role. However, the momentum seems to have evaporated somewhat in the meantime."

The PCI-SIG also caused a surprise with the very early announcement of PCI Express 6.0 and the goal to complete the corresponding specification by 2021. The pace is surprising, as the first PCIe 4.0 devices are just about to go into series production. "From my point of view PCIe 6.0 is much too early. We're just seeing that 3.0 is making inroads into the embedded market," explains Peter Ahne, Product Marketing Manager EMEA at Portwell Germany. This is also confirmed by Daniel Piper: "Almost all embedded customers currently manage without any problems with the bandwidth of the installed base such as PCI Express 3.0 in their applications - often only with 2.1, as with the popular i210 network controller.

In principle, however, the industry is open to the new standard. "The data hunger of IoT and KI requires a high throughput and fast storage media. Since in some interfaces such as M.2 the expansion is limited to further lanes, only a higher transfer rate per lane can increase the throughput. From the point of view of the embedded industry, this is the right approach," explains Josef Fromberger.

So far, the bandwidth of PCI Express has increased by doubling the symbol rate. As a result, the industry had to cope with ever higher frequencies in its assemblies and via the corresponding bus connectors. However, the symbol rate remains the same at the transition from 5.0 to 6.0, which means that higher frequencies do not have to be mastered. The bandwidth is doubled by a PAM-4 modulation of the signal, i.e. the transmission of two bits per clock. If a design masters PCIe 5.0, the transition to 6.0 should not cause any major problems from the physics point of view. An example of this could be COM-HPC, which is already based on PCIe 4.0 and 5.0 as the upcoming module standard (to be specified). "We are therefore optimistic to also support PCIe 6.0 with COM-HPC," emphasizes Christian Eder.

It will be years before the first PCIe 6.0 chips are available, after all there are not even PCIe 5.0 chips. The supply of the components of the current generations is much more urgent - last year the topic of allocation was unfortunately a long runner.

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