The step from research to industrial application can be a hurdle that should not be underestimated. Especially for industrial companies, adaptation to existing, established processes and quality standards poses challenges.
Prof. Robert Oshana, Vice President for Software Research and Development at NXP Semiconductors' Microcontrollers and Microprocessors Business Unit, has developed a practical approach to implementing the open instruction set architecture RISC-V. He will also speak on this topic at the embedded world Conference 2019. With his lecture »RISC-V; Practical Industry Approach to Getting Started with This Technology« he will open Session 5 »RISC-V« on February 26, 2019.
? Mr. Prof. Oshana, what is the biggest challenge for companies and designers/developers who want to develop a SoC with RISC-V for the first time?
! Robert Oshana: In many ways, implementing a RISC-V core is similar to the process to implement any other hardware IP.
- You want to make sure you have the right verification coverage for the IP.
- You want to make sure you have appropriate software support for the IP.
- And you want to make sure you have the right tools support for the IP.
If you go to a commercial RISC-V provider, you will be able to find all of this. If you want to use a community RISC-V core like PULPino, you may need to do some additional work to get the required software and tools for the core. If you are planning to extend the instruction set then you must have a plan for supporting the instruction extensions as well as testing/verifying them.
So having the appropriate emulation/FPGA environment for this analysis will be helpful.
The first time using a RISC-V core may require you to develop some additional support IP gaskets and shim layers to allow the core to easily integrate into the SoC with fewer modifications to the existing verification suite.
? How does the implementation of an open source architecture/IP differ from the implementation of commercial IPs?
! Oshana: RISC-V is an open specification, not implementation. But there are several commercial and community implementations available. Very similar to commercial and community distributions for Linux.
SiFive for example is a commercial RISC-V IP provider with some very innovative web based implementation models to allow a customer to »turn some knobs« to design and verify their own RISC-V based core.
ETH Zurich on the other hand has several community based RISC-V implementations available for no cost.
There is also a verification suite soon available that will allow a RISC-V user to verify their RISC-V core.
Implementing a RISC-V based design has been proven to be relatively straightforward for industry design teams. Just like in the open source software community, using open source technology is often times more reliable and robust than in house implementations.
? Can open hardware benefit from the experience gained with open software?
! Oshana: Yes absolutely. I have spoken about this often in my keynotes. Many of the best practices that have evolved from the open source software industry like Linux can be applied to open source hardware.
Just like there are 100’s of distributions for Linux, both commercial and community based, similar governance practices can be applied to RISC-V.
When we recently used the community based PULPino from RISC-V, we contributed IP back into the PULPino »main line« and this was carried forward into the next release, very similar to the way Linux works today.
There are some differences since RISC-V is an open specification and not an implementation, but many of the other practices are very similar.
? What is the best way to integrate open hardware like RISC-V into an existing development process?
! Oshana: We gained confidence in the ability to use RISC-V in an industry development environment by pipe-cleaning the process. We developed a RISC-V test chip as a way to validate that we could incorporate this IP into our existing development processes and environment.
Test chips are not always required, an FPGA platform could work as well. But being able to deploy a full device gave us confidence we could make use of this IP easily in our development environment.
It may be helpful to use an existing implementation for this. That’s what we did first.
Then after we gained more confidence in the IP we development our own »clean sheet« implementation which was completed ahead of time with high quality.
? What should companies and designers/developers be aware of when starting with open hardware and RISC-V?
! Oshana: One challenge is verification. We recommend developing the appropriate interface gaskets to allow a RISC-V core to be integrated into the SoC bus and interface structure.
This will allow the existing verification tests to be run without significant modification. Also since RISC-V allows for easy instruction extensions, care must be taken to provide for the associated compiler intrinsics or direct compiler support for these extensions.
Although there is a rapidly growing ecosystem for RISC-V, it makes sense to think about the tools support ahead of time and think about the appropriate debug architecture and interfaces early in the design cycle.
Finally, keep in mind the »non-core« parts of the design. The RISC-V core itself will be relatively easy to integrate, but it’s the non-core IP such as the interrupt controller, bus connections etc. where you want to put some focus.
Prof. Robert Oshana
Prof. Robert Oshana is VP of Software R&D for the Microcontroller and Microprocessor business line at NXP, responsible for software enablement, IoT connectivity, software middleware and security, operating systems, software services and advanced technologies.
He serves on multiple industry advisory boards and is a recognized international speaker. Prof. Oshana has published numerous books and articles on software engineering and embedded systems. He is also an adjunct professor at the University of Texas and Southern Methodist University and is a Senior Member of IEEE.