26. Januar 2021, 15:30 Uhr | Ralf Higgelke
Now let's move on to the manufacturing process itself. What are some of the challenges associated with a SiC process?
Agnes Jahnke: One might think that this is just as easy as with silicon wafers, but exactly the opposite is the case. Our engineers faced some enormous challenges before we were able to process SiC wafers with a yield similar to that of silicon wafers.
The processing of silicon carbide wafers (SiC) poses numerous challenges beyond of the challenges processing silicon wafers
First of all, silicon carbide is transparent and quite brittle. Therefore, we had to adapt a lot of equipment to handle, mark and measure SiC wafers.
A second challenge is the geometry of the SiC wafer. Compared to silicon wafers, they are highly curved and rough, but only half as thick. Imagine trying to put a bowl on a flat tray and lithographically introduce structures with the same focal depth over the entire wafer - you will fail. I mean, if you managed to suck the wafer to the wafer chuck beforehand, you will.
A third challenge stems from the physical difference of the crystal lattice of silicon carbide and silicon. With silicon, you implant the dopant on the surface, and diffusion creates the doped layer. However, this does not work with silicon carbide. There, practically no diffusion takes place, which means that the dopants remain where they have been implanted. To achieve the desired sheet resistance, the implanted layers must be heated. And it takes multiple, interlinked dopants to create a doping profile. That's why the implantation scheme is so critical to device properties. You basically have to shoot the atoms at the right angle, the right energy, the right dosage, and the right temperature to where you want them to be. So there's a lot of expertise hidden here, as you can imagine.
Implanting under such aggressive conditions creates a kind of crater landscape on the wafer. In order to be able to process the surface later on, it must therefore be healed with a high-temperature annealing process. This creates a carbonized surface on the wafer. And by high temperature, I mean really high temperatures! Silicon and other materials would simply melt at these 1800 degrees Celsius.
Are these the only challenges?
Agnes Jahnke: No. As you know, we are talking about power devices and that means a high current density through very thick metal layers on the surface of the semiconductor. On the other hand, the wafers for devices in the 600 volt to 1700 volt range have to be extremely thin. This is because the thinner the chip, the lower the on-resistance. Thick metal layers to conduct the high currents, however, put a lot of stress on SiC wafers.
And last but not least, there are challenges in component design. There is simply no perfect design, but only carefully balanced compromises between blocking voltage and on-resistance, for example.
To summarize, processing silicon carbide wafers in a silicon foundry is quite challenging. But we have succeeded. And I'm only talking about the technical issues, not the commercial ones, such as the lower throughput on most machines or the high wafer and substrate costs.
What are the advantages for semiconductor companies to work with a foundry like X-Fab?
Agnes Jahnke: First of all, our customers get exactly the device that meets their needs and in turn meets the requirements of their customers. They have the opportunity to develop the best SiC MOSFET or the most efficient power module the world has ever seen. And by working with X-Fab, they can achieve this goal faster. Ultimately, we make it easier for our customers to get started with this new wide bandgap material, and they can benefit from the economies of scale of a foundry, meaning lower cost per chip.
Together with our customers and partners we have realized silicon carbide devices with up to 10 kV breakdown voltage, very low on-state resistances or the highest current values in the industry.
Could you please be a little more specific about that?
Agnes Jahnke: Our tool set, processing capabilities, and design rules allow the first generation, for example, to realize MOSFETs with a cell pitch of five to about nine microns and a specific on-resistance of up to three milliohms by square centimeter. The next generation, which will require further expansion of the tooling, will follow the path to the theoretical limit and enable cell pitches as small as three microns or on-resistance as small as two miliohms by square centimeter. The specific characteristic values of the individual components depend on the individual design and can be adapted to customer requirements.
If you compare the data sheets of available SiC MOSFETs or the values from reverse engineering reports, you will see that we are already producing very competitive devices for our customers – with planar architecture.
What does the technology roadmap look like? Will X-Fab soon have SiC trench MOSFETs?
Agnes Jahnke: We are working on the second and third process generation as well as on trench technology. Further improvements will also be made in epitaxy, where we will be adding more capacity. In parallel, we are constantly developing new standard process blocks. In 2020, we added backside thinning to 110 microns, which is highly demanded, as well as a front side metallization that can be sintered.
Mrs. Jahnke, thank you very much for the interview.
The interview was conducted by Ralf Higgelke.