Interview about Open Source Hardware Instruction Set Architecture RISC-V

stilisierte CPU mit Lichteffekt
With RISC-V, the open source approach is to be transferred to hardware.

Open source software is popular – for operating systems as well as for office programs. But can this idea also work with hardware? We interviewed Rick O'Connor, Executive Director of the RISC-V Foundation.

?   Mr. O'Connor, what is RISC-V?

!   Rick O’Connor: RISC-V ISA is a free and open instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. RISC-V offers a number of advantages over other architectures, including its openness, simplicity, clean-slate design, modularity, extensibility and stability. Designers also have the option to implement extensions for RISC-V to optimize and customize a design for their specific application needs.

 

?   What advantages do you see through the use of RISC-V CPUs?

!   O’Connor: Implementers from a wide variety of industries are taking advantage of the flexibility, scalability and extensibility of RISC-V as an alternative to closed, proprietary ISAs. RISC-V has been designed into a wide variety of applications including graphics engines, machine learning and AI, networking, storage, security, embedded and general purpose processors. There’s also a growing ecosystem of OS support, development tools, FGPA softcores, IP and design services.

For example, to name but a few implementations from the vast RISC-V ecosystem,

  • Western Digital is transitioning consumption of over one billion cores per year to RISC-V to meet the needs of big data and fast data processing requirements.
  • Also, Microsemi created its Mi-V RISC-V ecosystem with a suite of tools and design resources from Microsemi and a number of third parties to support RISC-V design.
  • The French startup GreenWaves Technologies developed the industry’s lowest power IoT application processor, showing how a small team on a relatively limited budget can create custom embedded solutions.
  • The team at SiFive, consisting of original RISC-V pioneers out of UC Berkeley, are bringing the power of open-source and agile hardware design to the semiconductor industry with a variety of open RISC-V CPU implementations.

 

?   Are RISC-V CPUs compatible and how is compliance with the RISC-V Foundation's specification ensured?

!   O’Connor: The RISC-V ecosystem has demonstrated a large degree of interoperability among various implementations. The strategy behind RISC-V is to have a small simple base ISA and modular standard extensions that work well for the large majority of code, while also leaving ample space for application-specific extensions that do not interfere with the standard ISA core.

Also, the RISC-V Foundation has an active Compliance Task Group within the Technical Committee chartered with developing open source RISC-V ISA Compliance suites for use by all RISC-V implementers to validate ISA compliance.

 

?   What do Open Source License users need to consider when implementing the RISC-V ISA?

!   O’Connor: The RISC-V ISA if free and open for use by anyone in all types of implementations without restriction. Designers are free to develop proprietary implementations for commercial exploitation or open-source implementations to be shared as they see fit. The RISC-V Foundation encourages both types of implementations. For commercial RISC-V implementations, a license to the RISC-V trademarks is required which is granted to members of the RISC-V Foundation.

 

?   Who developed RISC-V?

!   O’Connor: RISC-V represents the fifth major RISC ISA design from UC Berkeley informed by more than three decades of RISC research dating back to Dave Patterson’s original RISC work in the 1980s. Dave Patterson and John Hennessy published the pioneering researched about RISC in Computer Architecture: A Quantitative Approach, a book that is now commonly known as the standard text for processor design.

In 2010, after many years and many projects using MIPS, SPARC, and x86 as basis of research, it was time for the Computer Science team at UC Berkeley to look at what ISAs to use for their next set of projects. Due to challenges with existing architectures, the team started a project to develop their own clean-slate ISA. In 2014, UC Berkeley released the fixed user spec for RISC-V. The RISC-V Foundation was officially founded in 2015 as a non-profit corporation to govern the ISA.

 

?   What are the objectives and tasks of the RISC-V Foundation?

!   O’Connor: The mandate of the RISC-V Foundation is to protect the sanctity of a single RISC-V standard across the industry and to encourage RISC-V ISA adoption globally.  The RISC-V ecosystem has seen incredible growth over the past few years. The RISC-V Foundation now has over 180 corporate, academic and individual members, directing the future development and adoption of the RISC-V ISA.

There are a number of innovative industry implementations of RISC-V from established technology giants and emerging startups, along with interesting applications from academic institutions and government-funded programs. With this growth, it’s clear that RISC-V is already paving the way for the next 50 years of computing design and innovation.

  

?   What are your plans for the future of the RISC-V Foundation?

!   O‘Connor: At the RISC-V Foundation, we look forward to seeing the RISC-V ecosystem mature even further as more companies join the Foundation and build new and innovative hardware and software that implements the ISA. The Foundation is also committed to developing more robust security approaches for the industry.

We recently created the Security Standing Committee bringing together industry leaders to share findings, develop consensus around best security practices and identify potential security improvements for RISC-V based IoT devices, embedded systems, and machine learning implementations.

We are also focused on increased Linux support for both embedded and compute distributions of the Linux OS. We expect to see closer collaboration with the Linux community, the most successful open source software ecosystem and RISC-V, the most widely adopted free and open ISA for use across all computing devices.

  

?   Was plant die RISC-V Foundation für die electronica in München?

!   O‘Connor: While the RISC-V Foundation will not be attending electronica in Munich this year, there are a variety of RISC-V activities happening at the show. Member companies including Dolphin Integration, GreenWaves Technologies and Microsemi will be exhibiting at the show.

 

Rick O‘Connor

ist geschäftsführender Direktor der RISC-V Foundation und der RapidIO.org. Mit seiner langjährigen Erfahrung in der Führungsebene von Halbleiterunternehmen verfügt er über eine einzigartige Kombination von kaufmännischen und technischen Fähigkeiten. O‘Connor war für die Entwicklung von Dutzenden von Produkten verantwortlich, die einen Umsatz von über 500 Millionen US-Dollar erzielten.

Er hat berufsbegleitend Betriebswirtschaft an der Universität Ottawa, Kanada, studiert (Executive MBA) und Elektrotechnik, B.A. (Hons), an der Hochschule Algonquin College in Ottawa, Kanada.

rickoco@riscv.org