This would be interesting because silicon technology is reaching its limits: It is becoming more and more expensive and difficult to further reduce the size of silicon-based transistors - and the theoretical limit is quickly approaching.
Many experts see a way out in carbon nanotube field effect transistors (CNFETs). They promise a factor of 10 higher energy efficiency and higher processing speeds than their silicon brothers. However, it has so far been difficult to produce the CNFETs in the required quality. Until now, they contained so many defects that they could not be used to build functional processors.
MIT researchers have now developed new manufacturing techniques that reduce the number of defects and allow the manufacturing process to be integrated into traditional CMOS processes. They demonstrated this using the example of a 16-bit processor with more than 14,000 CNFETs that could perform the same tasks as the traditional CMOS processors. The processor is built on a RISC-V architecture and could execute all commands properly. The number of CNFETs per area currently limits the length of the nanotubes, which can be significantly reduced compared to today, so that the packing density itself is not a problem.
"It is by far the most advanced chip ever introduced on the basis of an alternative technology and looks very promising for future energy-efficient high-performance computing," says Max M. Shulaker, Assistant Professor of Electrical Engineering and Computer Science (EECS) and member of Microsystems Technology Laboratories at MIT. "Carbon nanotubes are the most promising candidates to replace silicon technology. We have developed a completely new method to build chips with carbon nanotubes."
The new processor is based on a design that Shulaker and colleagues had already designed six years ago - but only with 178 NCFETs. Based on this, they have focused on three main areas for further research: Material defects, manufacturing defects and functional unit problems. His colleagues Gage Hill and Christian Lau took over the focus of processor design and manufacturing technology, respectively.
One of the biggest problems: A certain part of the CNs inevitably behaves metallically, which worsens their switching time or immediately prevents the switching process. A material purity of 99.999999 percent would be required to achieve the required quality - which is currently considered unattainable. The researchers' answer to this question is telling: DREAM. The abbreviation stands for "Designing Resilency against Metallic CNTs". This means that the metallic CNTs are introduced in such a way that they do not damage the actual calculation process. This enabled them to reduce the purity requirement by four powers of ten, so that the CNs now manage with only 99.99 percent.
The researchers found that the metallic CNs behave differently in different gate types. They now selected the different gate combinations, which proved to be robust in different combinations. The design program learns the optimal combinations automatically. When the program designs a new chip, it will therefore select the respective robust combinations. "We can now integrate standard CNs on the wafer and design the circuit as before without having to do anything special - really a dream."
The manufacturing process is roughly as follows: the CNs are applied in a solution to the wafer with prefabricated transistor structures. Inevitably, some CNs clump together - like small spaghetti balls - which act like dirt particles on the wafer. To clean up this contamination, the researchers developed RINSE (Removal of Incubated Nanotubes through Selective Exfoliation). The wafer is pretreated with a solution that improves CN adhesion. It is then provided with a polymer and immersed in a special solution. It removes the polymer that carries the large spaghetti balls. This leaves only the individual CNs on the wafer. This reduces the density of unwanted particles on the wafer by a factor of 250.
Until now it was also difficult to manufacture N and P transistors based on CNs. With the help of the also newly developed technology MIXED (Metal Interface Engineering Crossed with Electrostatic Doping), the researchers were able to overcome this difficulty. To do this, they combine the CNs with platinum and titanium in such a way that they behave like N- or P-type transistors. They then coat the CNFETs with an oxide compound via Atomic Layer Deposition. This allows them to tailor the transistors to specific characteristics. Servers, for example, require very fast switching transistors that are allowed to consume more power. Wearables and medical implants use slower transistors that consume less power.
The main goal is to bring the new process into the real world. To this end, the researchers are working with a traditional Fab with the support of the Defense Advanced Research Projects Agency (DARPA). When will such chips actually leave the fabs for real applications? According to Shulaker in less than five years: "It is no longer a question of whether, but only of when".