CSEM: 2.5 µW/MHz 32-bit controller with lowest power consumption

2.5 µW/MHz achieves a 32-bit RISC controller based on the new CSEM and MIFS technology. A complete design system including a Process Design Kit (PDK) with all libraries and key analog IP blocks is now available.
2.5 µW/MHz achieves a 32-bit RISC controller based on the new CSEM and MIFS technology. A complete design system including a Process Design Kit (PDK) with all libraries and key analog IP blocks is now available.

With a power consumption of only 2.5 µW/MHz, CSEM has set a world record for 32-bit RISC controllers.

The RSIC controllers are manufactured using a 55 nm CMOS process. CSEM has collaborated with wafer manufacturer Mie Fujitsu Semiconductor (MIFS) for this purpose. CSEM contributed its many years of experience in the development of ultra-low-power ASICs, MIFS its own power-saving (ELP) DDC technology.

The example of the 32-bit RISC controller, which is satisfied with a cable consumption of only 2.5 µW/MHz, shows what the combination of the two technologies can do. A complete Process Design Kit (PDK) and a range of silicon-tested mixed-signal IPs are now available. The controller operates at a near-threshold voltage of 0.5V. Lowering this voltage is critical because it is square in power consumption.

The lowest possible power consumption is essential for controllers to be used on the Internet of Things (IoT). The batteries should have a long service life and be as small as possible. This would make it possible to implement tiny sensor nodes with controllers and radio units that could operate autonomously over a longer period of time. It would be best if the batteries could be replaced or at least supplemented by energy harvesting units. Such tiny sensor nodes are therefore also referred to as "Smart Dust". With the new RISC processors, CSEM and MIFS have come one step closer to this vision. "The low-voltage design will be critical for future IoT devices," says Alain-Serge Porret, Vice-President Integrated & Wireless Systems at CSEM. A complete design system including a Process Design Kit (PDK) with all libraries and key analog IP blocks is now available.

A prerequisite for maintaining the low voltage values is the Deeply Depleted Channel (DDC) technology developed by MIFS. Its immunity to Random Dopant Fluctuation (RDF) makes DDC suitable for low voltage operation. However, low-voltage operation is also subject to process, temperature and other fluctuations. To reduce the effects of such variations, CSEM and MIFS have implemented a number of design techniques and a body bias-based Adaptive Dynamic Frequency Scaling (ADVbbFS) as one of the most important IPs.

"By combining CSEM's ULP technology with MIFS' DDC process technology, IoT chips can be developed that are unbeatable in energy efficiency," said Keizaburo Yoshie, senior vice president of MIFS.