Increasing efficiency and performance demands of portable and wearable electronics, along with their shrinking size in accordance with the Moore’s law, set new challenges to the power management of these devices as well. A solution is further integration of the devices’ key components into so-called SiP (systems-in-package) or SoC (systems-on-chip) architectures, where everything, including the energy storage such as batteries or capacitors, is packed close to each other into one compact, microscale-miniaturized assembly.
This calls for novel techniques to increase the performance and shrink the size of the energy storage unit as well. Three-dimensional, high aspect ratio and large surface area deep trench microcapacitors where ultra-thin, alternating layers of conducting and insulating materials form the energy storing structure, provide a potential solution.
Thanks to Picosun's ALD (Atomic Layer Deposition) technology, researchers at the University of Pisa led by Prof. Giuseppe Barillaro have now been able to achieve unprecedented performance of 3D microcapacitors. They have been able to deposit film stacks of conductive TiN and insulating dielectric Al2O3 and HfAlO3 layers into high aspect ratio (up to 100) trenches etched into silicon.
Up to 1 µF/mm² areal capacitance was obtained, which is due to the researchers a new record for this capacitor type. Also power and energy densities, 566 W/cm² and 1.7 µWh/cm², were excellent and surpassing the values achieved with the most of the other capacitor technologies. The ALD microcapacitors showed also outstanding voltage and temperature stability, up to 16 V and +100 °C, over 100 hours continuous operation, the researcher said. This could pave the way for commercial use of this capacitor technology, especially since ALD is available in all modern semiconductor manufacturing lines.
“We exploited the room available on the bottom of silicon wafers, of which only a few micrometers of silicon are used for electronic components in integrated circuits, to fabricate silicon-integrated 3D microcapacitors with unprecedented areal capacitance,” says Prof. Giuseppe Barillaro, group leader at the Information Engineering Department of the University of Pisa, Italy. He adds: “The electrochemical micromachining technology, developed at the University of Pisa over the past decade, enabled etching of high density trenches with aspect ratios up to 100 in silicon, a value otherwise not achievable with deep reactive ion etching. This posed the basis for increasing the areal capacitance of our 3D microcapacitors upon conformal coating with an ALD metal-insulator-metal stack”.
Lucanos M. Strambini, et al.: Three-dimensional silicon-integrated capacitor with unprecedented areal capacitance for on-chip energy storage, accepted for publication in Nano Energy, https://doi.org/10.1016/j.nanoen.2019.104281